This invention is in the field of analog-to-digital converter circuits. Embodiments of this invention are directed to error correction and compensation in such circuits.
Despite the continuing trend toward the digitization of electronic circuits and systems over recent years, modern electronic systems must still often process and generate electrical signals in the analog domain. For example, analog signals are transmitted and received in many modern communications technologies, and analog signals are used in instrumentation and control systems. Data converter circuits are therefore required to provide an interface between the digital and analog domains, especially in those systems in which digital signal processing is applied. As is fundamental in the art, analog-to-digital converters (ADCs) convert analog measurements or signals into the digital data to which digital signal processing is applied. Conversely, digital-to-analog converters (DACs) convert digital data into analog signals for transmission or actuation of a physical device.
Advances in modern data converter circuits have resulted in extremely precise, high-speed, data conversion functions. For example, ADCs with resolutions of from twelve to twenty-four bits, at sample rates up to tens of megasamples per second, are now available from Texas Instruments Incorporated. This level of performance requires not only very rapid switching speeds, but also an extremely high degree of precision. Accordingly, difficult tradeoffs are involved in the design of modern data converter circuits. Typically, the designer and manufacturer is faced with the three-way tradeoff among circuit complexity and cost, sample rate, and accuracy.
One well-known type of analog-to-digital converter is the so-called pipelined ADC, which will now be described relative to FIG. 1. In this example, the pipelined ADC has three stages 100 through 102, each of which will generate one or more digital bits corresponding to the amplitude of an analog input signal. First, or most significant, pipeline stage 100 receives the input analog signal at terminal ANALOG_IN, generates one or more digital bits on output D0, and also generates an analog residue that is presented to the next pipeline stage 101. Pipeline stage 101 similarly generates one or more digital bits on output D1 from this residue from stage 101, and generates an analog residue that is forwarded to the next pipeline stage 102. Stage 102 generates one or more digital bits on output D2 corresponding to the residue from stage 101, and forwards a residue to a next stage (not shown) if present. Digital outputs D0 through D2 are connected to digital correction function 11, which sum the digital bits from ADCs 3 into the eventual digital output on lines DIGITAL_OUT.
Pipeline stages 100 through 102 are similarly constructed as one another. In this conventional construction, with reference to stage 100 by way of example, the input to the stage is connected to the input of sample-and-hold circuit 2, which is clocked to receive and store an analog voltage corresponding to the voltage at that input. The output of sample-and-hold 2 is applied to the input of analog-to-digital converter (ADC) 3, and also to an input of analog adder 4. ADC 3 generates a digital output consisting of one or more bits on output line D0; this digital output is also applied to the input of digital-to-analog converter (DAC) 5. In many popular cases, the pipelined ADC generates “1.5” bits per stage 10, referring to each ADC 3 generating a two bit output, but with some of the bits digitally combined by digital correction function 11 to effect digital error correction, as known in the art. DAC 5 also receives this digital value, and in the conventional manner generates an analog signal that is subtracted from the analog input signal, by adder 4, to generate a residue signal that is forwarded to the next stage 101. This residue amounts to the difference between the input analog signal itself and an analog signal corresponding to the digital “integer” approximating the amplitude of the input analog signal; the next stage 101 thus digitizes this residue value to produce the next-most significant bit or bits. Gain stage 7 “gains up” the residue from adder 4, so that the residue analog signal will vary over the full input dynamic range of next stage 101, to avoid loss of sensitivity from stage to stage.
The conventional pipelined ADC approach of FIG. 1 provides some level of error correction in the analog-to-digital conversion process, as defined by the number of digital bits produced per stage and the number of stages, for a given level of precision (i.e., number of bits in the output word). In order to improve the error correction performance, however, the designer must either increase the number of pipeline stages, or increase the number of digital bits produced by each stage, either of which increases the circuit complexity and thus the cost, and may decrease the sample rate performance of the circuit.
Another conventional approach to improving the accuracy of analog-to-digital conversion is referred to in the art as “dithering”. Dithering addresses inaccuracy due to systematic error in the ADC. As known in the art, systematic error is error inherent in the particular circuit realization of the ADC function. One manifestation of systematic error in ADCs is reflected as differential nonlinearity (DNL), which is a measure of the difference between the actual analog step width between digital output values and the ideal value that step width (i.e., one LSB). Systematic error is also reflected by integral nonlinearity (INL), which is the deviation of the actual transfer function from the ideal straight line transfer function, over the full-scale range. According to this technique, pseudo-random noise is added to the analog signal prior to analog-to-digital conversion, with the noise effects subtracted from the digital output in the digital domain to remove both the effects of random noise and also some of the systematic error of the ADC. However, the dithering technique necessarily introduces additional overhead circuitry into the analog interface, specifically by the circuitry required to inject the random noise into the input signal path.
By way of further background, post-conversion digital compensation of dynamic error in the ADC process, particularly dynamic errors in the track and hold function within typical ADC stages, is also a known technique. According to this approach, during calibration of the ADC, a digital signal processor extracts model parameters for the track-and-hold function. These model parameters are then applied by the digital signal processor by way of a digital compensation transfer function. However, the non-linear compensation function necessarily inserts significant computational burden on the digital circuitry, as evident by the necessity of a digital signal processor to derive and apply that compensation.
By way of further background, time-interleaved ADC circuits are known in the art. According to this architecture, multiple ADC circuits all receive the same input analog signal, but are operated in a time-interleaved fashion to produce a high data rate digital output. Each ADC can thus operate at a much lower speed than the eventual output data stream.